2025.04.07In intelligent security and video analytics, the HiSilicon Hi3403V100 is rapidly becoming the next-generation engine for AI vision. Integrating high-performance video codecs with an AI inference engine, it processes multi-stream HD video while running complex recognition and analysis at low power. Neardi’s core module, dev board, and embedded AI box let enterprises quickly build end-to-end solutions—from front-end capture to edge intelligence—for smart surveillance, industrial inspection, smart retail, and more.
HiSilicon Hi3403V100 (21AP10) is a highly-integrated SoC purpose-built for intelligent video and edge computing. It combines quad Cortex-A55 CPU + MCU + DSP + dual-core NPU in a heterogeneous architecture, delivering up to 10.4 TOPS@INT8 AI inference while integrating dedicated depth-compute and image-acceleration blocks for high efficiency and low power. The chip supports up to 8-K video encode/decode, multi-channel 4-K input and stitching, and incorporates an advanced ISP with full-suite enhancements including WDR, 3-D NR, HDR and fisheye correction. Rich I/O—PCIe, USB 3.0, dual Gigabit Ethernet, MIPI/HDMI/DSI—covers multi-camera to HD display. With ~5 W typical power and a complete SDK, Hi3403V100 enables high-performance, low-latency AI-vision deployment in security, industrial vision and smart retail.
| Category | Key Parameters |
| CPU | Quad-core ARM Cortex-A55 @ 1.4 GHz (32 KB I/D-Cache per core, 512 KB L3, Neon & FPU) |
| MCU | 32-bit @ 500 MHz (32 KB I/D-Cache, 64 KB TCM) |
| Security | TrustZone (REE/TEE), secure boot |
| AI Acceleration | 10.4 TOPS INT8 dual-core heterogeneous NPU (4.8 TOPS + 5.6 TOPS), dual Vision-Q6 DSP, dedicated depth & matrix HW |
| Video Encode | H.264/H.265/JPEG up to 8192×8192; example: 4K@60 fps + 720p@30 fps or 8K@15 fps |
| Video Decode | H.264/H.265/MPEG-4/JPEG; example: 4K@60 fps + 1080p@60 fps; JPEG 4K@75 fps, max 16 K×16 K |
| Rate Control | Max 160 Mbps, CBR/VBR/AVBR/FIXQP/QPMAP, 8 ROI, 8 OSD |
| Video Input | 8-lane MIPI/LVDS/Sub-LVDS/HiSPi (2×4-lane or 4×2-lane, ≤ 4 sensors), max 8192×8192, 150 MHz |
| ISP | 3A, 3F WDR, local tone mapping, multi-level 3-D NR, de-haze, edge/contrast enhance, defect-pixel & lens correction, 6-DoF EIS, rolling-shutter correction, HNR, 3-D-LUT, PC tuning tool |
| Video Output | HDMI 2.0, 4-lane MIPI DSI/CSI (2.5 Gbps/lane), CVBS, 8/16/24-bit RGB, BT.656/BT.1120; dual independent HD outputs; max 4096×2160@60 fps + 1920×1080@60 fps; 1/15.5–16× scaling, 4-sensor panorama stitch, overlay, CSC |
| Audio | 16-bit on-chip codec, I2S (TDM), HDMI audio; SW codecs G.711/G.726/AAC with 3A (AEC/ANR/ALC) |
| DRAM | DDR4 4×16-bit (≤ 3200 Mbps) or LPDDR4/LPDDR4x 2×32-bit (≤ 3733 Mbps), max 8 GB |
| Flash/Storage | SPI NOR/NAND, parallel NAND (SLC/MLC, 8–64-bit ECC), eMMC 5.1 ≤ 2 TB; boot from eMMC, SPI NOR/NAND, NAND, or PCIe slave |
| High-Speed I/O | 2× USB3.0/USB2.0 (USB0 host, USB1 host/dev), 2-lane PCIe 2.0 (RC/EP, splittable) |
| Network | 2× Gigabit Ethernet (RGMII/RMII, TSO/UFO/COE, jumbo) |
| Other Peripherals | 2× SDIO 3.0 (SDXC 2 TB + Wi-Fi), multiple UART/I2C/SPI/GPIO, 4-ch LSADC, IR, PWMs |
| Package & Power | 23 mm × 23 mm FC-BGA, 0.65 mm pitch, RoHS; core 0.8 V, I/O 1.8 V/3.3 V, DDR4 1.2 V, LPDDR4 1.1 V, LPDDR4x 0.6 V; typical 5.2 W (4K30 + 4 TOPS) |
| SDK | Linux SMP on A55, LiteOS on DSP/MCU; production-ready SDK for fast mass-production |
LCH3403V100
LKD3403V100
LBA3403V100
LPA3403V100
Tel
Email
Address